In portable electronic devices, such as mobile communication devices, reducing power consumption is one of the key requirements in the respective integrated circuit design. One of the methods for reducing the power consumption is using dual operation mode, in which the normal operation of the integrated circuit may use a normal power supply voltage VDD that is high enough to drive the integrated circuit to achieve required high performance. In other operations not demanding high performance, a gated-VDD may be used to provide power to the integrated circuit. Under the gated-VDD that is lower than power supply voltage VDD, less power is consumed. The gated-VDD, although causing the degradation in the performance of the integrated circuit, is not an issue in certain operations, such as in the power down mode or standby mode.
FIG. 1 illustrates a conventional circuit capable of providing both power supply voltage VDD and a gated-VDD. Power supply line 10 carries power supply voltage VDD. Low-leakage mode control pin 14 is connected to the gate of PMOS transistor 18. Low-leakage mode control pin 14 determines whether SRAM array 12 should operate under power down/standby mode or normal operation mode. The voltage at low-leakage mode control pin 14 determines whether PMOS transistor 16 will be activated to reduce the power supply voltage provided to SRAM cell 12. The gate and the drain of PMOS transistor 16 are interconnected so that PMOS transistor 16 functions as a diode. Accordingly, PMOS transistor 16 is also referred to as a bias transistor.
A difficulty in the design and manufacturing of the circuit as shown in FIG. 1 is ensuring that PMOS transistor 16 has adequate voltage drop while at the same time providing adequate current to SRAM array 12. However, these two requirements often conflict with each other. Accordingly, a greater design margin is needed, which results in the increase in design and manufacturing costs, such as the increase in chip area usage.